Virtual prototyping of a synthetic aperture radar processor and RASSP benchmark 1

A virtual prototype of a synthetic aperture radar processor is being created by Lockheed Sanders. It includes VHDL models and Ada application code. The virtual prototype is a behavioral and structural model which matches the hardware architecture which was selected as part of this effort. A s part of the RASSP program, we are answering the question: "How can one use VHDL to validate hardware / sofhvare trade-offs and reduce the l i f . cycle cost of digital systems?" The current status is that the virtual prototype has been completed and we are now entering into a hardware prototype phase which will validate the virtual prototype.